The present invention is related to improved computer-aided methods for creating integrated circuits and, more particularly, to computer-aided methods for design, verification, implementation, and signoff of Application-Specific Integrated Circuits (ASICs).
A customer typically approaches a foundry to make an ASIC according to the customer's specifications. The customer's specifications may include input/output (I/O), timing diagrams, state machines, power and thermal requirements, clocking, floorplan area, and Hardware Description Language (HDL) source code. HDL is a programming language that is used to model digital systems at many levels of abstraction ranging from the algorithmic level to the gate level. The complexity of the digital system may vary from that of a simple gate to a complete digital electronic system, or anything in between.
The production of an ASIC is generally performed in two phases: a design phase and an implementation phase. In the design phase, design engineers at the foundry work with the customer to develop the behavioral specifications for the ASIC. Depending on the information provided by the customer, the design engineers may have a very active role in the development of the behavioral specifications. Once the design phase is completed, the design engineers pass the behavioral specifications and other information to implementation engineers at the foundry. The process of passing control from the design phase to the implementation phase is called the design signoff ("signoff"). During the implementation phase, the implementation engineers produce a gate level specification of the ASIC and perform other functions (e.g., layout) required to produce the ASIC.
Throughout the design and implementation phases, HDL has many uses including behavioral specification, gate level specification, and implementation of test benches. There are many different flavors of HDL for modeling digital systems. VHSIC HDL ("VHDL") was developed for the Department of Defense and has subsequently been standardized by the IEEE and ANSI. Verilog HDL is another flavor of HDL that is used in one embodiment of the invention. Although there are different variations of HDL, each has the capability of modeling digital systems at both the behavioral and structural (e.g., gate) level. HDL may also be used to implement a test bench which is a model that is used to simulate and verify the correctness of an HDL hardware model. HDL provides the capability of writing test benches in the same language that describes the hardware.
The present scale of integration (VLSI and ULSI) allows for entire systems to reside on a single chip. However, the design tools and methods that allow for newer levels of integration on a mass scale have traditionally lagged behind the ASIC technology. Currently, there is a need for new tools and methods that improve design, implementation and signoff for larger-scale levels of integration. The present invention fulfills this and other needs.